Due to the increasing difficulty in shrinking complementary metal-oxide-semiconductor (CMOS) transistor gate lengths while simultaneously controlling leakage current, the traditional single-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure (where the inversion layer is formed only in the plane of the wafer surface) may be supplanted by dual- or triple-gate MOSFET structures. These structures, by increasing the gate's control of the channel potential, allow greater ability to turn off MOSFETs with ultra-short channel lengths. Of the various multi-gate MOSFETs structures explored in recent years, the most promising in terms of manufacturability and performance are typically variations of the so-called “FinFET” structure; these variations are known by such terms as “Tri-gate,” “Omega-FET,” or “MuGFET.” Generally, for each of these device types, a strip or “fin” of silicon (Si) is formed; subsequently the gate material is deposited and etched, so that the resulting gate surrounds the fin on the three exposed sides. The channel region of the device is located in the fin. To introduce strain into such a strip or fin, researchers have explored process-inducement methods similar to those employed in single-gate MOSFETs, such as, for example, epitaxially raised silicon germanium (SiGe) or silicon carbide (SiC) source and drain regions. There are, however, limitations to such methods, including limitations on how much strain can be introduced into the channel.